Referenced Items are not available for this document.
This paper compares reduced complexity sequence estimation (RCSE) algorithms in terms of SNR performance, VLSI implementation, hardware complexity and critical path. A novel architecture is presented which reduces the hardware complexity of RCSE and relaxes the critical path problem. This architecture can be used to implement RCSE for Gigabit Ethernet 1000Base-T
Published in:
VLSI Technology, Systems, and Applications, 1999. International Symposium on
Date of Conference: 1999
- Page(s):
- 171 - 174
- Meeting Date :
- 08 Jun 1999-10 Jun 1999
- Print ISBN:
- 0-7803-5620-9
- INSPEC Accession Number:
- 6504360
- Conference Location :
- Taipei
- Digital Object Identifier :
- 10.1109/VTSA.1999.786027
- Product Type:
- Conference Publications
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