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DSP-based real-time video decoding

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2 Author(s)
Minhua Zhou ; DSP Solutions R&D Center, Texas Instrum. Inc., Dallas, TX, USA ; Talluri, R.

In this paper we describe the implementation of MPEG4/H.263 real-time video decoding on the high performance fixed-point DSP. This series of DSP utilize a common core based on VelociTI/sup TM/, the advanced very long instruction word (VLIW) DSP architecture, which makes them ideal for the high performance embedded multimedia applications. On the EVM board of this kind of DSP (CPU frequency 160 MHz) we were able to demonstrate decoding of MPEG-4/H.263 bitstream coded at 700 Kbps, CIF (352/spl times/288), at a speed of 55/65 fps, respectively. Applications such as consumer set-top boxes that decode streaming video on the Internet and packet-based videophones will benefit from this performance.

Published in:

Consumer Electronics, 1999. ICCE. International Conference on

Date of Conference:

22-24 June 1999

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