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A single chip digital TV LSI with a flexible 2D graphic processor utilizing an optimized memory architecture

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4 Author(s)
Yamada, M. ; Toshiba Corp., Yokohama, Japan ; Tomonaga, E. ; Lin, M. ; Hung, J.

A single chip digital TV LSI including MPU, transport decoder, MPEG audio/video decoder, and graphic processor is described. This LSI utilizes dedicated RISC processors and advanced unified memory architecture with special arbitration algorithm, which enables optimal memory access operation.

Published in:

Consumer Electronics, 1999. ICCE. International Conference on

Date of Conference:

22-24 June 1999