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We have developed a 2" multilayer HTS process that contains four epitaxial layers (3 superconducting and one dielectric) and up to 4 additional non-epitaxial layers. Employing n-factorial and Taguchi designed experiments, we have improved crossover critical currents by 45/spl times/ and via critical currents by 60/spl times/. We use the DOE approach to quantitatively compare processing factors and identify those which are electrically significant. Transmission Electron Microscopy confirms the morphological changes which cause the electrical response. This article highlights the history of our multilayer process, using both TEM and electrical results to show how process modifications have led to a robust multilayer process for HTS circuit applications.