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Electrical evaluation of flip-chip package alternatives for next generation microprocessors

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6 Author(s)
J. Darnauer ; Juniper Networks, Mountain View, CA, USA ; D. Chengson ; B. Schmidt ; E. Priest
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Two styles of flip-chip packages for next-generation microprocessors were designed: a low-cost organic ball-grid-array (BGA) and a thin-film-on-ceramic land-grid array (LGA). Simultaneous switching output (SSO) noise, and core noise were measured. Although SSO was improved by a factor of two over the previous generation of packaging, core noise was still quite significant. We found that core noise is best managed by placing low-inductance capacitance close to the noise source, i.e., using on-chip capacitors, coupled planes in the package, or on-package bypass capacitors. Because of the lower impedance of its power planes, the ceramic package showed significantly better electrical performance than the organic. Addition of on-package bypass capacitors greatly narrows the gap between the two packages

Published in:

IEEE Transactions on Advanced Packaging  (Volume:22 ,  Issue: 3 )