A memory-based architecture for MPEG2 system protocol LSIs

This paper proposes a memory-based architecture implementing the MPEG2 system protocol large scale integrations (LSIs), and demonstrates its flexibility and performance. The memory-based architecture implements the full functionality of the MPEG2 system protocol for both multiplexing and demultiplexing MPEG2-encoded streams. It consists of a core central processing unit, memories, and dedicated application-specific hardware. It is designed and optimized by hardware/software codesign techniques. The LSI's provide sufficient performance and flexibility for real-time application of the MPEG2 system protocol. They were fabricated with 0.5 /spl mu/m CMOS embedded gate array process technology. They are now in use on MPEG2 codec systems for several multimedia communication and storage services.