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We present two versions of self-timed pipelined parallel carry-look-ahead adders. The adders are designed based on delay-insensitive (DI) rapid single-flux-quantum (RSFQ) primitives. Basic binary gates employ dual-rail encoded data, which include timing information in themselves. One version uses wave pipelining and the other delay-insensitive pipelining with a request-acknowledge data transfer protocol. We show simulation results of 4 to 32-bit adders and their sensitivity to delay variations. Two design schemes are compared in terms of area, speed, robustness, interface and design process for large systems.