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A reentrant delay-line memory using a YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// coplanar delay-line

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3 Author(s)
Hattori, W. ; Fundamental Res. Labs., NEC Corp., Tsukuba, Japan ; Yoshitake, T. ; Tahara, S.

The rapid growth in telecommunication traffic demands a higher-speed asynchronous transfer mode (ATM) switching system. At present, the upper limit of the system clock rate is determined by the maximum clock rate of conventional semiconductor memory devices, such as the register files used in ATM cell buffer storage. This is because the maximum clock rate of these register files is restricted by the propagation delay time between each register stage. Since a reentrant superconducting delay-line memory avoids this restriction using an analogue delay given by the superconducting delay line, we have proposed that this memory should be used in high-speed ATM cell buffer storage. Recently, we fabricated a 10-/spl mu/m-wide 37-cm-long YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// coplanar delay-line. This line had a delay of approximately 2.8 ns. Using this coplanar delay-line and an assembly of commercially available integrated circuits, we successfully developed superconducting delay-line memory. This memory operates as a 32-bit buffer storage at a clock rate of 10 GHz, which is several times faster than the register files. This result shows that the superconducting delay-line memory is a powerful candidate for high-speed ATM cell buffer storage.

Published in:

Applied Superconductivity, IEEE Transactions on  (Volume:9 ,  Issue: 2 )