By Topic

High-speed decimation filter for delta-sigma analog-to-digital converter

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
Xie, Y.P. ; Dept. of Electr. Eng. & Comput. Sci., California Univ., Berkeley, CA, USA ; Whiteley, S.R. ; Van Duzer, T.

A 12-bit digital filter is designed for an A/D converter system with sampling speed of 16 GHz. Data stream of 16 Gbit/s from delta-sigma modulator will pass through a 1:4 demultiplexer. Four identical 12-bit digital filters are used to catch the data streams from the demultiplexer for 4 Gbit/s in each channel. The 12-bit superconductive digital filter is designed with modified variable threshold logic (MVTL) gates. A novel XOR gate is designed and used in this circuit to reduce circuit complexity and improve performance. Progress of high speed testing results is presented. The filter comprises 584 Josephson junctions and consumes about 1 mW power.

Published in:

Applied Superconductivity, IEEE Transactions on  (Volume:9 ,  Issue: 2 )