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Low T/sub c/ superconductive circuits fabricated on 150-mm-diameter wafers using a doubly planarized Nb/AlO/sub x//Nb process

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4 Author(s)
Berggren, K.K. ; Lincoln Lab., MIT, Lexington, MA, USA ; Macedo, E.M. ; Feld, D.A. ; Sage, J.P.

We have used a doubly planarized all-refractory technology for superconductive electronics (DPARTS) process to fabricate mixed-signal circuits that have more than 200 junctions per circuit and operate at 2 GHz. A 150-mm-diameter wafer can produce more than 400 chips, each 5 mm on an edge. The junctions had a critical current density of 1.7 kA/cm/sup 2/. The wafers were evaluated at room temperature, both in- and post-process. In-process testing was used to detect parameter shifts during processing, while post-process testing used an automated testing station to test more than 3500 structures across each completed wafer and thus establish a large set of statistical data for studying the spread and targeting of parameter values. The circuits were fabricated in a class-10 clean room in which 0.25 /spl mu/m CMOS and CCD devices were also produced. The DPARTS process could also be used for sub-/spl mu/m fabrication, as it includes optical lithography with an i-line stepper; chemical-mechanical planarization at two levels; a self-aligned via process; and dry, anisotropic etching for all metal etching and via definition steps. The use of 150-mm-diameter wafers ensures that this process will be able to exploit technological advances in the standard silicon tool set as improvements become available. The results demonstrated here are a necessary precondition to yielding large volumes of superconductive electronic circuits containing devices with sub-/spl mu/m dimensions.

Published in:

Applied Superconductivity, IEEE Transactions on  (Volume:9 ,  Issue: 2 )