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We have designed and fabricated test structures that allow the determination of the critical current density and processing run-out of low T/sub c/ Josephson junctions based only on room-temperature measurements. We demonstrated that the 300 K tunneling conductance of a junction barrier is proportional to the critical current at 4.2 K. This testing technique greatly reduced the time required to characterize a process wafer. In one demonstration we tested hundreds of devices across a 150-mm-diameter wafer in less than an hour. In another we used a selective niobium anodization process with only two mask levels to determine the critical current density of a Nb/AlO/sub x//Nb trilayer within a day of its deposition. We have also used automated probing stations to decrease testing delays further and thus to improve process cycle time.