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Determining redundancy requirements for memory arrays with critical area analysis

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6 Author(s)

Using in-line defect data, critical area analysis of cell layout, and a rule-based algorithm to associate critical areas with electrical faults, we can determine the optimum redundancy configuration for any memory circuit. The technique predicts the yield for a range of redundancy configurations and finds the optimum number of redundant rows and columns for any memory design based on yield and die size considerations

Published in:

Memory Technology, Design and Testing, 1999. Records of the 1999 IEEE International Workshop on

Date of Conference:

1999