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A fault-tolerant array processor designed for testability and self-reconfiguration

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4 Author(s)
Jain, A. ; Dept. of Electr. Eng., McGill Univ., Montreal, Que., Canada ; Mandava, B. ; Rajski, J. ; Rumin, N.C.

The design of a fault-tolerant rectangular array of processing elements (PEs) is presented in which the reconfiguration is done by means of on-chip distributed logic, without the help of any external host. Spare PEs are included in every column of the array, and faulty PEs are bypassed within a column to facilitate reconfiguration in the presence of faults. Scan paths are used to enhance the testability of the array. PEs are tested locally using near-neighbor comparisons without the need of an external host. Because the interconnections between logical neighbors are short, the speed penalty for reconfiguration is very small. Any amount of redundancy can be incorporated in the array without changing the topology of the scheme or the design of the reconfiguration switches. The scheme is well suited for very large-area, high-density chips and wafer-scale integration. In order to demonstrate the capabilities of the scheme and evaluate its performance, an experimental chip consisting of a 6×4 array was designed, fabricated, and tested. Details of the design and the implementation of the chip are presented. The scheme is also analyzed for yield and area utilization for a range of array sizes and PE survival probabilities

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:26 ,  Issue: 5 )

Date of Publication:

May 1991

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