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Multiple-level partitioning: an application to the very large-scale hardware simulator

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3 Author(s)
Y. -C. Wei ; Dept. of Comput. Sci. & Eng., California Univ., San Diego, La Jolla, CA, USA ; C. -K. Cheng ; Z. Wurman

With modern technology, a very-large-scale system may contain several million gates. To achieve an optimal multiple-level partitioning of such a system onto a fixed hierarchy hardware accelerator presents a formidable challenge to even the fastest computing engines currently available. The application of a divide-and-conquer heuristic coupled with a novel ratio-cut algorithm that solves the above problem under a variety, of constraints is described. The goal of this approach is to minimize the communication cost in the hierarchy. Experiments with designs containing up to two million gates are described, and it is demonstrated that the proposed approach decreased communication costs by a factor of two or more when compared with other approaches. This approach enables the hardware simulator to perform approximately three billion gate evaluations per second. or approximately 200 million event evaluations in an event-driven simulator, using a 6% activity rate

Published in:

IEEE Journal of Solid-State Circuits  (Volume:26 ,  Issue: 5 )