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Noise-aware repeater insertion and wire sizing for on-chip interconnect using hierarchical moment-matching

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2 Author(s)
Chung-Ping Chen ; Strategic CAD Labs., Intel Corp., Hillsboro, OR, USA ; N. Menezes

Recently, several algorithms for interconnect optimization via repeater insertion and wire sizing have appeared based on the Elmore delay model. Using the Devgan noise metric a noise-aware repeater insertion technique has also been proposed recently. Recognizing the conservatism of these delay and noise models, we propose a moment-matching based technique to interconnect optimization that allows for much higher accuracy while preserving the hierarchical nature of Elmore-delay-based techniques. We also present a novel approach to noise computation that accurately captures the effect of several attackers in linear time with respect to the number of attackers and wire segments. Our practical experiments with industrial nets indicate that the corresponding reduction in error afforded by these more accurate models justifies this increase in runtime for aggressive designs which is our targeted domain. Our algorithm yields delay and noise estimates within 5% of circuit simulation results

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Design Automation Conference, 1999. Proceedings. 36th

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