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Memory exploration for low power, embedded systems

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2 Author(s)
Wen-Tsong Shiue ; Dept. of Electr. Eng., Arizona State Univ., Tempe, AZ, USA ; C. Chakrabarti

In embedded system design, the designer has to choose an on-chip memory configuration that is suitable for a specific application. To aid in this design choice, we present a memory exploration strategy based on three performance metrics, namely, cache size, the number of processor cycles and the energy consumption. We show how the performance is affected by cache parameters such as cache size, line size, set associativity and tiling, and the off-chip data organization. We show the importance of including energy in the performance metrics, since an increase in the cache line size, cache size, tiling and set associativity reduces the number of cycles but does not necessarily reduce the energy consumption. These performance metrics help us find the minimum energy cache configuration if time is the hard constraint, or the minimum time cache configuration if energy is the hard constraint

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Design Automation Conference, 1999. Proceedings. 36th

Date of Conference: