By Topic

CAD directions for high performance asynchronous circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

7 Author(s)
Stevens, K. ; Strategic CAD Labs., Intel Corp., Hillsboro, OR, USA ; Rotem, S. ; Burns, S.M. ; Cortadella, J.
more authors

This paper describes a novel methodology for high performance asynchronous design based on timed circuits and on CAD support for their synthesis using relative timing. This methodology was developed for a prototype iA32 instruction length decoding and steering unit called RAPPID (“revolving asynchronous Pentium processor instruction decoder”) that was fabricated and tested successfully. Silicon results show significant advantages-in particular, performance of 2.5-4.5 instructions per nS-with manageable risks using this design technology. RAPPID achieves three times faster performance and half the latency dissipating only half the power and requiring a minor area penalty as a comparable 400 MHz clocked circuit. Relative timing is based on user-defined and automatically extracted relative timing assumptions between signal transitions in a circuit and its environment. It supports the specification, synthesis, and verification of high-performance asynchronous circuits, such as pulse-mode circuits, that can be derived from an initial speed-independent specification. Relative Timing presents a “middle-ground” between clocked and asynchronous circuits, and is a fertile area for CAD development. We discuss possible directions for future CAD development

Published in:

Design Automation Conference, 1999. Proceedings. 36th

Date of Conference:

1999