Space compaction for multiple-output circuits

A counting signature for multiple-output circuits is introduced. It implements both time compaction and space compaction, such that a single signature is derived for all outputs, using a simple scheme with suitable built-in implementation. It is shown that there exists testability criteria that show deterministically at design time, without full-fault simulation, whether a fault is testable by the signature. The computation of such criteria is straightforward, can be easily incorporated into a CAD system such that the testability results are directly available to the designer. The best current application of such a space-compacted signature is to PLAs (programmable logic arrays) and ROMs (read-only memories), where full testability of all single faults is achieved. Discussion, results, proofs, and examples are presented, including an initial comparison with multiple-input shift registers (MISRs).<
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