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Design of high-performance CMOS charge pumps in phase-locked loops

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1 Author(s)
W. Rhee ; Conexant Syst. Inc., Newport Beach, CA, USA

Practical considerations in the design of CMOS charge pumps are discussed. The non-ideal effects of the charge pump due to the leakage current, the mismatch, and the delay offset in the P/FD are quantitatively analyzed. To use the appropriate charge pump in various PLL applications, several architectures are investigated and their performances are compared. The improved design of both the single-ended and the differential charge pumps are presented with the simulation result

Published in:

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on  (Volume:2 )

Date of Conference:

Jul 1999