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High speed interface for system-on-chip design by self-tested self-synchronization

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2 Author(s)
Fenghao Mu ; SwitchCore, Lund, Sweden ; Svensson, C.

Global synchronization has been commonly used to protect clocked I/O from data read failure due to metastability. For future high performance system-on-chip design, global synchronization is more difficult as both frequency and chip size increase quickly. This paper addresses a mesochronous clocking (MC) strategy which can be implemented with three self-tested self-synchronization (STSS) methods for parallel data transfer between processing elements (PEs). Compared with global synchronization, MC has many advantages: lower process cost; less power dissipation in clock distribution; no limit in system scale; less delay in long distance data transfer; more simplicity and flexibility in design. The STSS implementations are also very simple and robust, and the metastability in data read is avoided because STSS is completely insensitive to both clock skew and data delay

Published in:

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on  (Volume:2 )

Date of Conference:

Jul 1999