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Capacitor mismatch error cancellation technique for a successive approximation A/D converter

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5 Author(s)
Zhiliang Zheng ; Dept. of Electr. & Comput. Eng., Oregon State Univ., Corvallis, OR, USA ; Un-Ku Moon ; Steensgaard, J. ; Wang, B.
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An error cancellation technique is described for suppressing capacitor mismatch in a successive approximation A/D converter. At the cost of a 50% increase in the conversion time, the first order capacitor mismatch error is cancelled. Methods for achieving top-plate parasitic insensitive operation are described, and the use of a gain- and offset-compensated op amp is explained. SWIT-CAP simulation results show that the proposed 16-bit SAR ADC can achieve an SNDR of over 91 dB under nonideal conditions, including 1% 3σ nominal capacitor mismatch, 10-20% randomized parasitic capacitors, 66 dB op amp gain, and 30 mV op amp offset

Published in:

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on  (Volume:2 )

Date of Conference:

Jul 1999