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A CMOS RMS-to-DC converter using ΔΣ multiplier-divider

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2 Author(s)
Wei-Shinn Wey ; Inst. of Electron., Nat. Chiao Tung Univ., Hsinchu, Taiwan ; Yu-Chung Huang

A novel topology for CMOS ΔΣ RMS-to-DC converters is described. Analysis shows that the proposed topology is insensitive to most circuit imperfections except offset voltages. A test circuit of a 1st-order single-ended RMS-to-DC converter is realized in a 0.8 μm double-poly CMOS process. Experimental results demonstrate that input waveforms with crest factors as high as 3 can be measured at the 800 mV full-scale input level. It provides a maximum relative error of ±1% of reading

Published in:

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on  (Volume:2 )

Date of Conference:

Jul 1999