Design and implementation of a CMOS power feedback linearization IC for RF power amplifiers

This paper describes an integrated circuit design and implementation of a simple and partly new RF power amplifier linearization system based on power feedback. The prototype linearization IC using a standard double-metal double-poly 0.8 /spl mu/m CMOS process was fabricated and tested. When it was used to linearize an efficient power amplifier transmitting a /spl pi//4-shifted DQPSK modulated North American Digital Cellular (NADC) signal, experimental results showed that a reduction of more than 10 dB in the adjacent channel interference was achieved. The chip, which occupies 1.9 mm/sup 2/ with pads, operates with 5 V supply voltage and measured power consumption is 65 mW.