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Design and implementation of a CMOS power feedback linearization IC for RF power amplifiers

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2 Author(s)
Bo Shi ; Dept. of Appl. Electron., Lund Univ., Sweden ; Sundström, L.

This paper describes an integrated circuit design and implementation of a simple and partly new RF power amplifier linearization system based on power feedback. The prototype linearization IC using a standard double-metal double-poly 0.8 μm CMOS process was fabricated and tested. When it was used to linearize an efficient power amplifier transmitting a π/4-shifted DQPSK modulated North American Digital Cellular (NADC) signal, experimental results showed that a reduction of more than 10 dB in the adjacent channel interference was achieved. The chip, which occupies 1.9 mm2 with pads, operates with 5 V supply voltage and measured power consumption is 65 mW

Published in:

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on  (Volume:2 )

Date of Conference:

Jul 1999

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