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Cost-effective co-verification using RTL-accurate C models

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1 Author(s)
Jain, P.P. ; CAE Plus Inc., Austin, TX, USA

The verification quality of a system on chip (SOC) design depends on the number of simulations that can be performed under time-to-market constraints. This in turn depends on both the simulation speed and the cost of multiple simulator licenses. Since HDL simulators are both slow and expensive, design quality suffers. This paper presents a methodology and associated tools for the use of RTL-accurate C models for fast and cost-effective verification

Published in:

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on  (Volume:6 )

Date of Conference:

Jul 1999