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A constraint-based placement refinement method for CMOS analog cell layout

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5 Author(s)
X. Zeng ; Dept. of Electr. Eng., Fudan Univ., Shanghai, China ; J. Guan ; W. Q. Zhao ; P. S. Tang
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The performance of analog circuits is sensitive to fabrication process and the layout of their physical masks. In this paper, a novel constraint-based methodology is proposed for the placement refinement of CMOS analog cell circuits. Constraint-based module generation and shaping process are also developed not only to optimize the layout shape, area but more importantly to guarantee the analog circuits performance. A hybrid-tree model is proposed to simultaneously represent the geometry, symmetry and parasitic constraints for the layout. Experimental results have shown the effectiveness of the proposed method

Published in:

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on  (Volume:6 )

Date of Conference:

Jul 1999