By Topic

On VLSI decompositions for deBruijn graphs

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

3 Author(s)
T. Yamada ; Dept. of Phys. Electron., Tokyo Inst. of Technol., Japan ; S. Imai ; S. Ueno

A VLSI decomposition of a graph G is a collection of isomorphic vertex-disjoint subgraphs (called building blocks) of G which together span G. This paper gives a necessary condition and a sufficient condition for a graph to be a building block for deBruijn graphs, which are used to build Viterbi decoders

Published in:

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on  (Volume:6 )

Date of Conference:

Jul 1999