By Topic

A memory addressing and access design for real time volume rendering

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

2 Author(s)
Doggett, M. ; Tubingen Univ., Germany ; Meissner, M.

This paper presents a memory addressing design that uses buffering to achieve a cache hit ratio of 95% for a PCI based Volume Rendering hardware accelerator. The target system for this memory interface is VIZARD II, a second generation PCI board using several XILINX chips. To improve the performance of this and possibly other hardware accelerators, a cubic addressing scheme is presented that improves the percentage of cache hits to misses. To further improve the performance the cubic addressing is coupled with several FIFO buffers to minimise the pipeline stalling effect of cache misses in the eight parallel memory modules. This combination of addressing scheme and memory access buffering raises the cache hit to miss ratio from 63% to 95%. Most Volume Rendering systems are fully pipelined and can utilise the design presented here to increase the number of frames per second and the quality of rendered images

Published in:

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on  (Volume:4 )

Date of Conference:

Jul 1999