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A speculative multithreading with selective multi-path execution

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3 Author(s)
Kanemitsu, O. ; Utsunomiya University, Japan ; Wataru, Y. ; Fumihito, F.

Recent microprocessors' performance has been improved by their high-speed clock frequency and by their exploiting instruction-level parallelism (ILP). Physical limitations of clock speed and semantical limitations of control dependencies impede the improvement of performance. To overcome this dificulty, it is indispensable to make use of the thread-level parallelism. This paper proposes a speculative thread execution model that aims at a speed-up of sequential program execution by selective multi-path thread execution.

Published in:

Innovative Architecture for Future Generation High-Performance Processors and Systems, 1998

Date of Conference:

24-24 Oct. 1998

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