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Efficient VLSI architecture for 2-D inverse discrete wavelet transforms

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2 Author(s)
Chu Yu ; Dept. of Electr. Eng., Nat. Taiwan Univ., Taipei, Taiwan ; Sao-Jie Chen

In this paper, we present a high-performance VLSI architecture for 2-D inverse discrete wavelet transforms (IDWT). The architecture is designed based on a computation-schedule scheme to process the input signals in real-time, and uses two efficient filter structures to minimize the hardware cost. For the computation of an N×N 2-D image with a filter length L, this architecture spends nearly N2 clock cycles, and requires about NL storage unit, 3½L multipliers, as well as 7(L/2-1)+4 adders

Published in:

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on  (Volume:3 )

Date of Conference:

Jul 1999