A distributed memory and control architecture for 2D discrete wavelet transform

A distributed memory and control architecture for parallel computation of the 2D discrete wavelet transform is proposed. The architecture is systolic and is obtained by performing a thorough data dependence and localization analysis for the 2D discrete wavelet transform. The design is modular, and can easily be scaled for different levels of wavelet decomposition and filter lengths. The derived architecture for an 8/spl times/8 image has been functionally verified and a chip layout has been obtained in Cadence.