Referenced Items are not available for this document.
We review trends in interconnect bandwidth requirements for multiprocessor systems and technologies proposed to meet these requirements. The benefits and costs of core-based optoelectronic chips are discussed using CMOS-SEED implementations of the WARRP network router as a case study. Results indicate that transistor density and on-chip clock rates of optoelectronic core-based designs can be reduced by as much as 40% and 30%, respectively, but aggregate off-chip bandwidth can be increased by as much as an order of magnitude as compared to all-electronic chip designs
Published in:
Selected Topics in Quantum Electronics, IEEE Journal of
(Volume:5
,
Issue:
2
)
Date of Publication: Mar/Apr 1999
- Page(s):
- 330 - 338
- ISSN :
- 1077-260X
- INSPEC Accession Number:
- 6340313
- Digital Object Identifier :
- 10.1109/2944.778317
- Product Type:
- Journals & Magazines
- Date of Current Version :
- 06 August 2002
- Issue Date :
- Mar/Apr 1999
- Sponsored by :
- IEEE Photonics Society
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