Referenced Items are not available for this document.
In this paper, we address the issues of designing low power VLSI implementation of the Viterbi decoder. We propose a new VLSI architecture for carrying out the add-compare-select (ACS) operation for the Viterbi decoder which can reduce the complexity of the computation. Also a novel pre-computational architecture is proposed to further reduce the power consumption of the ACS unit
Published in:
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
(Volume:1
)
Date of Conference: Jul 1999
- Page(s):
- 137 - 140 vol.1
- Meeting Date :
- 30 May 1999-02 Jun 1999
- Print ISBN:
- 0-7803-5471-0
- INSPEC Accession Number:
- 6382163
- Conference Location :
- Orlando, FL
- Digital Object Identifier :
- 10.1109/ISCAS.1999.778000
- Product Type:
- Conference Publications
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