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Design and implementation of an RSA public-key cryptosystem

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3 Author(s)
Jyh-Huei Guo ; Dept. of Electr. Eng., Nat. Tsing Hua Univ., Hsinchu, Taiwan ; Chin-Liang Wang ; Hung-Chih Hu

This paper presents a new bit-serial systolic array for realizing a modified Montgomery algorithm for modular multiplication. The proposed array is highly regular, modular, and thus well suited to be implemented using VLSI techniques. It does not involve any broadcasting signals and thus can be operated at a higher clock rate than existing designs. A VLSI architecture for modular exponentiation, which can be used to implement the encryption, decryption, and digital signature of an RSA public-key cryptosystem, is also constructed based on the proposed modular multiplier. For the purpose of verification, a prototype chip of a 512-bit RSA public-key cryptosystem is designed based on the high-performance COMPASS 0.6 μm standard cell library. The gate count of the chip is about 132 k and the die size is about 8280 μm×8224.8 μm. With an estimated clock rate of 143 MHz, a baud rate of 2781 k bits/sec can be achieved

Published in:

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on  (Volume:1 )

Date of Conference:

Jul 1999