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An efficient probabilistic method for logic circuits using real delay gate model

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5 Author(s)
Theodoridis, G. ; Dept. of Electr. & Comput. Eng., Patras Univ., Greece ; Theoharis, S. ; Soudris, D. ; Stouraitis, T.
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Our goal is the development of a novel probabilistic method to estimate accurately the power consumption of a logic level circuit under real delay model generalising fundamental principles of zero delay-based methods. Based on Markov stochastic processes, a set of new formulas, which describe the temporal and spatial correlation in terms of the associated zero delay-based parameters, under the real delay model, are introduced. The chosen gate model allows accurate estimation of the functional and spurious (glitches) transitions, leading to accurate power estimation. A comparative study of benchmark circuits demonstrates the accuracy of the proposed method

Published in:

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on  (Volume:1 )

Date of Conference:

Jul 1999