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A new high-speed/low-power dynamic CMOS logic and its application to the design of an AOI-type ROM

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2 Author(s)
Ching-Rong Chang ; Dept. of Electr. Eng., Nat. Chung-Cheng Univ., Taiwan ; Jinn-Shyan Wang

A new high-speed and low-power dynamic CMOS logic named NHS-PDCMOS logic is proposed. An AOI-type ROM designed in NHS-PDCMOS logic is found to have enhanced speed and power performance than that designed in quasi-domino technique. The power and cycle-time product of the NHS-PDCMOS ROM is only 20.9% that of the quasi-domino ROM

Published in:

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on  (Volume:1 )

Date of Conference:

Jul 1999