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Architecture of a hardware module for MPEG-4 shape decoding

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3 Author(s)
Berekovic, M. ; Inst. fur Theor. Nachrichtentech. und Inf., Hannover Univ., Germany ; Jacob, K. ; Pirsch, P.

MPEG-4 shape coding comprises context based binary arithmetic encoding (CAE) as its centerpiece. The architecture of a dedicated hardware acceleration module for CAE shape decoding is presented. Synthesis with a 3LM 0.5 μ CMOS library provides a size estimate of 9200 gates plus 3 KB of ROM, which equals approximately 5 mm2 silicon area. The module achieves a throughput rate of 63 MPixel/s

Published in:

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on  (Volume:1 )

Date of Conference:

Jul 1999