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Low power DCT implementation approach for VLSI DSP processors

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2 Author(s)
Masupe, S. ; Dept. of Electron. & Electr. Eng., Edinburgh Univ., UK ; Arslan, T.

This paper presents an algorithm for the low power implementation of the discrete cosine transform on single multiplier CMOS DSPs. The algorithm reduces power by a combination of using shift operations, where possible, and manipulating bit-correlation between successive cosine coefficients applied to the input of the multiplier section such that the effective switched capacitance is reduced. This reduces the switching activity in the multiplication of a discrete cosine transform processor. The paper describes the algorithm, the evaluation procedure and presents results with a number of example images illustrating up to 50% power savings

Published in:

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on  (Volume:1 )

Date of Conference:

Jul 1999