VLSI implementation of a multicast ATM switch

In this paper, VLSI design of a multicast ATM switch controller is presented. The ATM switch system is based on the shared multibuffer architecture. The cyclic queue algorithm is used at the address queues to increase the throughput, and no memory speed up is needed. By employing the multicast queue and dynamic multicast scheme, multicast functions can be efficiently carried out and the hardware complexity is reduced. The 8/spl times/8 switch is designed to handle the OC-12 (622 Mbps) transmission rate. The switch controller is designed by using a 0.6 /spl mu/m single-poly triple-metal CMOS technology. Simulation results show that the chip can correctly operate at 40 MHz.