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VLSI implementation of a multicast ATM switch

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3 Author(s)
R. C. Chang ; Dept. of Electr. Eng., Nat. Chung-Hsing Univ., Taichung, Taiwan ; Lung-Chih Kuo ; Chih-Yuan Hsieh

In this paper, VLSI design of a multicast ATM switch controller is presented. The ATM switch system is based on the shared multibuffer architecture. The cyclic queue algorithm is used at the address queues to increase the throughput, and no memory speed up is needed. By employing the multicast queue and dynamic multicast scheme, multicast functions can be efficiently carried out and the hardware complexity is reduced. The 8×8 switch is designed to handle the OC-12 (622 Mbps) transmission rate. The switch controller is designed by using a 0.6 μm single-poly triple-metal CMOS technology. Simulation results show that the chip can correctly operate at 40 MHz

Published in:

Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on  (Volume:1 )

Date of Conference:

Jul 1999