Referenced Items are not available for this document.
A good verification strategy should bring near the simulation and real functioning environments. In this paper we describe a system-level co-verification strategy that uses a common flow for functional simulation, timing simulation and functional debug. This last step requires using a BST infrastructure, now widely available on commercial devices, specially on FPGAs with medium/large pin-counts
Published in:
Circuits and Systems, 1999. ISCAS '99. Proceedings of the 1999 IEEE International Symposium on
(Volume:1
)
Date of Conference: Jul 1999
- Page(s):
- 35 - 38 vol.1
- Meeting Date :
- 30 May 1999-02 Jun 1999
- Print ISBN:
- 0-7803-5471-0
- INSPEC Accession Number:
- 6382140
- Conference Location :
- Orlando, FL
- Digital Object Identifier :
- 10.1109/ISCAS.1999.777799
- Product Type:
- Conference Publications
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