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An efficient bus architecture for system-on-chip design

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1 Author(s)
Cordan, B. ; Palmchip Cor., Loveland, CO, USA

This paper presents the issues confronted when integrating system-on-chip (SOC) designs and offers solution through a detailed description of the CoreFrameTM system-on-chip bus architecture that has dramatically reduced system design and verification effort while enhancing the reusability and customizability of system-on-chip product developments. The CoreFrame on-chip bus architecture is defined along with examples to illustrate how a design friendly bus standard will effect the mix and match of reusable cores without sacrificing performance

Published in:

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Date of Conference: