By Topic

A low-power direct digital frequency synthesizer architecture for wireless communications

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Bellaouar, A. ; VLSI Res. Group, Waterloo Univ., Ont., Canada ; Obrecht, M. ; Fahim, A. ; Elmasry, M.I.

A novel low-power direct digital frequency synthesizer (DDFS) architecture is presented. The sine and cosine functions are generated by linearly interpolating between the sample points, reducing the size of the ROM look-up table to 416 bits for 9-bit output resolution. The DDFS is implemented in 0.8 μm CMOS technology and features 60 dBc spectral purity, 48 Hz frequency resolution, with only 9.5 mW (@30 MHz, 3.3 V) power dissipation

Published in:

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Date of Conference: