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A low-power direct digital frequency synthesizer architecture for wireless communications

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4 Author(s)
Bellaouar, A. ; VLSI Res. Group, Waterloo Univ., Ont., Canada ; Obrecht, M. ; Fahim, A. ; Elmasry, M.I.

A novel low-power direct digital frequency synthesizer (DDFS) architecture is presented. The sine and cosine functions are generated by linearly interpolating between the sample points, reducing the size of the ROM look-up table to 416 bits for 9-bit output resolution. The DDFS is implemented in 0.8 μm CMOS technology and features 60 dBc spectral purity, 48 Hz frequency resolution, with only 9.5 mW (@30 MHz, 3.3 V) power dissipation

Published in:

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Date of Conference:

1999

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