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Switching well noise analysis and minimization strategy for low V th CMOS integrated circuits

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5 Author(s)
Koyama, A. ; Device Dev. Center, Hitachi Ltd., Tokyo, Japan ; Tsuge, M. ; Kudo, J. ; Aida, T.
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An accurate equation and solution to estimate switching well noise in CMOS integrated circuits with low Vth is proposed. The propagation characteristics of the noise are fully analyzed with a distributed parameter model, which enables us to derive a novel design guideline and layout strategy to minimize switching well noise

Published in:

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

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