By Topic

Clock verification in the presence of IR-drop in the power distribution network

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$31 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Hussain, S.Z. ; Simplex Solutions Inc., Sunnyvale, CA, USA ; Rochel, S. ; Overhauser, D. ; Saleh, R.

Clock nets are the most important circuits in high-speed digital systems. The design of clock circuitry and the quality of the clock signal directly impacts the performance of a VLSI chip. Clock verification requires high accuracy and is typically performed using circuit simulators. In high-performance deep-submicron digital circuits, clocks are running at higher frequencies and are driving more gates than ever, thus presenting a higher load on the power distribution network with the potential of substantial IR-drop. However, as IR-drop is a full-chip phenomenon, circuit simulation is extremely time consuming. In this paper, we present a loosely coupled iterative technique for clock verification in the presence of full-chip dynamic IR-drop. The degradation in the clock signal due to dynamic IR-drop is demonstrated on a small example as well as upon a large chip. In addition, we also discuss risks associated with assuming a static IR-drop budget upon clock propagation

Published in:

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Date of Conference:

1999