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A CMOS mixed-signal 100 Mb/s receive architecture for fast Ethernet

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4 Author(s)
A. Shoval ; Lucent Technol., Allentown, PA, USA ; O. Shoaei ; K. O. Lee ; R. H. Leonowich

A 125 Mbaud quad transceiver for 10/100 fast Ethernet has been designed in a 5 V 0.35 μm digital CMOS process. Power consumption for the device is 3 W. Detailed testing show excellent receiver results with error free performance up to 160 m under worst-case baseline wander and crosstalk conditions. The analog receiver uses digital adaptation circuitry to optimize an automatic gain control circuit with baseline wander correction, an equalizer and a DC offset correction circuit

Published in:

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

Date of Conference:

1999