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Flexible reconfigurable multiplier blocks suitable for enhancing the architecture of FPGAs

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3 Author(s)
S. D. Haynes ; Dept. of Electr. & Electron. Eng., Imperial Coll. of Sci., Technol. & Med., London, UK ; A. B. Ferrari ; P. Y. K. Cheung

A new architecture is proposed for configurable blocks which can be used to dynamically construct multipliers. An array of these blocks is capable of being configured to perform any 8m by 8n bits signed/unsigned binary multiplication. The new design is based on the radix-4 overlapped multiple-bit scanning algorithm. This yields excellent multiplication times, at the same time allowing multiply accumulate (MAC) operations, without modification. The new design is compared to our previous scheme, and shown to be both faster and require fewer transistors

Published in:

Custom Integrated Circuits, 1999. Proceedings of the IEEE 1999

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