By Topic

High-frequency four noise parameters of silicon-on-insulator-based technology MOSFET for the design of low-noise RF integrated circuits

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

6 Author(s)
G. Dambrine ; Dept. Hyperfrequences et Semicond., IEMN, Villeneuve d'Ascq, France ; J. -P. Raskin ; F. Danneville ; D. Vanhoenackel Janvier
more authors

An exhaustive experimental study of the high-frequency noise properties of MOSFET in silicon-on-insulator (SOI) technology is presented. Various gate geometries are fabricated to study the influence of effective channel length, gate finger width, and gate sheet resistivity on the four noise parameters. The high level of MOSFET sensitivity to the minimum noise matching condition is demonstrated. From experimental results, optimal ways to realize ultra low noise amplifiers are discussed. The capability of the fully depleted standard SOI CMOS process for realizing low-noise amplifiers for multigigahertz portable communication systems is shown

Published in:

IEEE Transactions on Electron Devices  (Volume:46 ,  Issue: 8 )