By Topic

An asymmetrically doped buried-layer (ADB) structure for low-voltage mixed analog-digital CMOS LSI's

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
M. Miyamoto ; Device Dev. Center, Hitachi Ltd., Tokyo, Japan ; K. Toyota ; K. Seki ; T. Nagano

A new CMOS structure has been developed that is distinguished by its asymmetrically doped buried layer (ADB). This structure makes it possible to achieve high drain output resistance and high transconductance necessary for high-performance analog circuits with a low-voltage power supply. The ADB structure has a high-impurity-concentration “pocket” layer near the channel edge of the buried layer only on the source side and a low-impurity surface region through the channel. The source-side channel region determines the threshold voltage and the drain-side channel region absorbs the drain potential. The low-impurity surface region reduces impurity scattering and enables high transconductance. The fabricated ADB CMOS structure increased the drain output resistance, transconductance, and saturation current down to a 0.3-μm channel length, as compared to a control structure. Furthermore, the drain junction capacitance was reduced because of the low impurity concentration beneath the drain region

Published in:

IEEE Transactions on Electron Devices  (Volume:46 ,  Issue: 8 )