By Topic

Low-power dynamic termination scheme using NMOS diode clamping

Sign In

Cookies must be enabled to login.After enabling cookies , please use refresh or reload or ctrl+f5 on the browser for the login options.

Formats Non-Member Member
$33 $13
Learn how you can qualify for the best price for this item!
Become an IEEE Member or Subscribe to
IEEE Xplore for exclusive pricing!
close button

puzzle piece

IEEE membership options for an individual and IEEE Xplore subscriptions for an organization offer the most affordable access to essential journal articles, conference papers, standards, eBooks, and eLearning courses.

Learn more about:

IEEE membership

IEEE Xplore subscriptions

4 Author(s)
Dong-Ho Shin ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea ; Young-Min Lee ; Kyu-Hyoun Kim ; Kwyro Lee

An NMOS diode clamped termination (NDCT) with NMOS threshold voltage (Vth) of around 0 V is proposed as a dynamic termination for a high-speed/low-power chip-to chip interconnection scheme. Both simulation and experimental results for several benchmark circuits show that, compared with open termination, the magnitudes of both overshoot and undershoot for nanosecond-range input pulses are typically less than ~15% of supply voltage (Vcc=3.3 V) with the same order of magnitude in power saving. Finally, the NDCT is found to be very immune to electrostatic discharge, guaranteeing more than 3000 V for a human body model. Our results demonstrate the potentiality of NDCT as a high-speed interconnection scheme

Published in:

IEEE Journal of Solid-State Circuits  (Volume:34 ,  Issue: 8 )