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Low-power dynamic termination scheme using NMOS diode clamping

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4 Author(s)
Dong-Ho Shin ; Dept. of Electr. Eng., Korea Adv. Inst. of Sci. & Technol., Seoul, South Korea ; Young-Min Lee ; Kyu-hyoun Kim ; Kwyro Lee

An NMOS diode clamped termination (NDCT) with NMOS threshold voltage (Vth) of around 0 V is proposed as a dynamic termination for a high-speed/low-power chip-to chip interconnection scheme. Both simulation and experimental results for several benchmark circuits show that, compared with open termination, the magnitudes of both overshoot and undershoot for nanosecond-range input pulses are typically less than ~15% of supply voltage (Vcc=3.3 V) with the same order of magnitude in power saving. Finally, the NDCT is found to be very immune to electrostatic discharge, guaranteeing more than 3000 V for a human body model. Our results demonstrate the potentiality of NDCT as a high-speed interconnection scheme

Published in:

Solid-State Circuits, IEEE Journal of  (Volume:34 ,  Issue: 8 )

Date of Publication:

Aug 1999

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