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Gigabit-per-second, ECL-compatible I/O interface in 0.35-μm CMOS

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3 Author(s)
H. Djahanshahi ; Dept. of Electr. & Comput. Eng., Toronto Univ., Ont., Canada ; F. Hansen ; C. A. T. Salama

This paper presents high-speed differential input and output (I/O) interface circuits for gigabit-per-second serial data communication. The circuits are implemented in a 3.3-V/0.35-μm CMOS process. Signal levels are compatible with industry standards for low-voltage positive emitter-coupled logic (ECL), with the possibility of ac-coupling to standard ECL systems. A differential open-drain circuit with pulsed bias and active pullups offers significantly improved speed performance for a transmitter and creates wide open eye patterns. Combining circuit techniques with the features of a submicrometer technology, the presented I/O blocks enable a full-CMOS chip to communicate with high-speed ECL-compatible systems and ease up a common I/O-related speed bottleneck. The circuits operate at 622 Mb/s (OC-12) and 1.24 Gb/s (OC-24) in a repeater and a retimer configuration. The asynchronous performance of the receiver and the transmitter was tested at rates up to 2.5 Gb/s

Published in:

IEEE Journal of Solid-State Circuits  (Volume:34 ,  Issue: 8 )