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Performance trade-offs for microprocessor cache memories

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2 Author(s)
Alpert, D.B. ; Nat. Semicond. Corp., Herzliya, Israel ; Flynn, M.

Design trade-offs for integrated microprocessors caches are examined. A model of cache utilization is introduced to evaluate the effects on cache performance of varying the block size. By considering the overhead cost of sorting address tags and replacement information along with data, it is found that large block sizes lead to more cost-effective cache designs than predicted by previous studies. When the overhead cost is high, caches that fetch only partial blocks on a miss perform better than similar caches that fetch entire blocks. This study indicates that lessons from mainframe and minicomputer design practice should be critically examined to benefit the design of microprocessors.<>

Published in:

Micro, IEEE  (Volume:8 ,  Issue: 4 )